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Product Attributes

Introduction

The TMS44C256 series are high-speed, 1,048,576-bit DRAMs organized as 262,144 words × 4 bits. Fabricated using advanced EPIC (Enhanced Planted CMOS) technology, they deliver high performance, high reliability, and low power consumption at low cost. Maximum RAS access times are 60 ns, 70 ns, 80 ns, 100 ns, and 120 ns. Maximum power dissipation is as low as 305 mW in active operation for the 120 ns device, and only 1 μW in standby.

EPIC technology enables single 5 V supply operation, reducing system power and decoupling requirements while simplifying board layout. Typical peak ICC is 140 mA, and the devices can tolerate input voltage undershoot of −1 V, minimizing system noise concerns. All inputs and outputs, including clocks, are compatible with 54/74-series TTL. All address and data inputs are latched on-chip to simplify system design. Data outputs are unlatched for increased system flexibility.

The TMS44C256 is available in a 20-pin DIP (N suffix), 20-pin zigzag in-line package (SD suffix), 20/26 J-lead plastic SOJ (DJ suffix), and 20/26 J-lead thin plastic SOJ (DN suffix). The TMS44C256-60 and TMS44C256-70 are available only in the 20/26 J-lead plastic SOJ (DJ suffix). All packages are guaranteed for operation over the 0°C to 70°C temperature range.

Features

• 262144 x 4 organization
• Single 5V supply (±10% tolerance)
• Speed options:
  • TMS44C256-60: Read cycle 60ns, access time 15ns/30ns, write cycle 110ns
  • TMS44C256-70: Read cycle 70ns, access time 18ns/35ns, write cycle 130ns
  • TMS44C256-80: Read cycle 80ns, access time 20ns/40ns, write cycle 150ns
  • TMS44C256-10: Read cycle 100ns, access time 25ns/45ns, write cycle 180ns
  • TMS44C256-12: Read cycle 120ns, access time 30ns/55ns, write cycle 220ns
• Enhanced page mode operation with CAS-before-RAS refresh
• Extended refresh period: 512-cycle refresh within 8ms maximum
• Three-state non-latching outputs
• Low power consumption
• Texas Instruments EPIC CMOS process
• All inputs and clocks TTL-compatible
• High-reliability plastic 20-pin 300-mil wide DIP, 20/26 J-lead surface mount (SOJ) ('44C256-60 and '44C256-70 available in SOJ only), 20/26 J-lead Thin Small Outline (ThinSOJ), or 20-pin Zigzag Inline Package (ZIP)
• Texas Instruments megabit CMOS DRAM operation controllable via TI SN74ALS6301 and SN74ALS6302 dynamic RAM controllers
• Operating temperature: 0°C to 70°C