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Product Attributes

Introduction

The 'ALS6301 and 'ALS6302 dynamic memory controllers (DMCs) are designed for use in today's high-performance memory systems. The DMC acts as the address controller between any processor and dynamic memory array. Two versions are provided that help simplify interfacing to the system dynamic timing controller. The 'ALS6301 offers active-low Row Address Strobe Input (RASI) and Column Address Strobe Input (CASI), while the 'ALS6302 offers active-high Row Address Strobe Input (RASI) and Column Address Strobe Input (CASI) inputs. Using two 10-bit address latches, the DMC will hold the row and column addresses for any DRAM up to 1M. These latches and the two row/column refresh address counters feed into a 10-bit, 4-input MUX for output to the dynamic RAM address lines. A 2-bit bank select latch is provided to select one of the four RAS and CAS outputs. The two bits are normally obtained from the two highest-order address bits. The 'ALS6301 and 'ALS6302 have two basic modes of operation, read/write and refresh. During normal read/write operations, the row and column addresses are multiplexed to the dynamic RAM, with the corresponding RAS and CAS signals activated to strobe the addresses into the RAM. In the refresh mode, the two counters cycle through the refresh addresses. If memory scrubbing is not being implemented, only the row counter is used. When memory scrubbing is being performed, both the row and column counters are used to perform read - modify - write cycles. In this mode all RAS outputs will be active (low) while only one CAS output is active at a time. The DMC is designed with heavy - duty outputs that are capable of driving four banks of 16 - bit words, including six checkbits used for error detection and correction. In addition to heavy - duty output drivers, the outputs are designed with balanced output impedances (25 Ω both high and low). This feature optimizes the drive low characteristics, based on safe undershoot, while providing symmetrical drive high characteristics. It also eliminates the external resistors required to pull the outputs up to the Mos level. With a 10 - bit address path, the DMC can control up to four megaword when using 1M dynamic RAMs. If a larger memory size is desired, the DMC's chip select (CS) makes it easy to expand the memory size by using additional DMCs. The two 10 - bit counters in the 'ALS6301 and 'ALS6302 support 128 -, 256 -, 512 -, and 1024 - line refresh operations. Transparent, burst, synchronous, or asynchronous refresh modes are all possible.

Features

• Provides Control for 16K, 64K, 256K, and 1M Dynamic RAMs
• Highest - Order Two - Address Bits Select One of Four Banks of RAMs
• Supports Scrubbing Operations and Nibble Mode Access
• Separate Output Enable for Multi - Channel Access to Memory
• 52 - Pin Dual - ln - Line Package