مدار مجتمع (آی سی) آی‌سی منطقی (دیجیتال) حافظهٔ فایفو

RENESAS 72V01L25JGI8

Manufacturer	RENESAS
Mfr. Part Number	72V01L25JGI8
Electland Part Code	764750
Electland Part Number	NYE_72V01L25JGI8
Category	FIFOs Memory
Description	Asynchronous FIFO 4.5K (512 x 9) Uni-Directional 28.5MHz 25ns 32-PLCC (14x11.46)

Product Attributes

Category	Integrated Circuits (ICs) Logic FIFOs Memory
Memory Size	512x9
function	Asynchronous
Data Rate	28.5MHz
Access Time	25ns
Voltage - Supply	3V~3.6V
Current - Supply (Max)	60mA
Bus Directional	Unidirectional
Expansion Type	Depth, Width
Programmable Flags Support	No
Retransmit Capability	Yes
FWFT Support	No
Operating Temperature	-40℃~+85℃
Mounting Type	Surface Mount
Package / Case	32-LCC (J-Lead)
Supplier Device Package	32-PLCC (14x11.46)
Features	Automatic retransmission function
Clock Frequency	28.5MHz
Current - Supply(Max)	60mA
Packaging	PLCC-32(11.5x14)
Tariff Active	True
ReachStatus	REACH Unaffected
RohsStatus	ROHS3 Compliant
MoistureSensitivityLevel	3 (168 Hours)
ExportControlClassNumber	EAR99
HtsusCode	8542.32.0071
Weight	8.8g

Introduction

The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO memories operating at a supply voltage (Vcc) between 3.0V and 3.6V. Their architecture, functional operation, and pin assignments are identical to those of the IDT7201/7202/7203/7204/7205/7206. These devices load and unload data in a first-in, first-out manner. They use full and empty flags to prevent data overflow and underflow, and employ expansion logic to allow unlimited expansion in both word width and depth.

Read and write operations are performed internally in sequence via circular pointers, loading and unloading data without requiring address information. Data is clocked through the device via the Write (W) and Read (R) pins. The maximum data access time is as fast as 25ns.

These devices use a 9-bit-wide data array, allowing the user to select control bits or parity bits. This feature is particularly useful in data communications applications where parity bits are required for transmit/receive error checking. They also include a Retransmit (RT) function, which allows the read pointer to be reset to its initial position when the RT pulse is driven low, enabling retransmission of data from the beginning. A half-full flag is available in both single-device mode and width expansion mode.

These FIFOs are fabricated using high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read and write operations in multiprocessing and rate-buffering applications.