مدار مجتمع (آی سی) آیسی تعبیهشده (پردازنده) افپیجیای
AMD/XILINX XC9536XL-10VQG44I
| Manufacturer | AMD/XILINX |
|---|---|
| Mfr. Part Number | XC9536XL-10VQG44I |
| Electland Part Code | 720298 |
| Electland Part Number | |
| Category | FPGAs (Field Programmable Gate Array) |
| Description | LQFP-44(10x10) FPGAs (Field Programmable Gate Array) RoHS |
Product Attributes
| Category | Integrated Circuits (ICs) Embedded FPGAs (Field Programmable Gate Array) |
|---|---|
| Number of I/O | 34 |
| Number of Gates | 800 |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Package / Case | 44-TQFP |
| Supplier Device Package | 44-VQFP (10x10) |
| Programmable Type | In System Programmable (min 10K program/erase cycles) |
| Voltage Supply - Internal | 3V ~ 3.6V |
| Number of Logic Elements/Blocks | 2 |
| Number of Macrocells | 36 |
| Delay Time tpd(1) Max | 10 ns |
| Packaging | LQFP-44(10x10) |
| Tariff Active | True |
| ReachStatus | REACH Unaffected |
| RohsStatus | ROHS3 Compliant |
| MoistureSensitivityLevel | 3 (168 Hours) |
| ExportControlClassNumber | EAR99 |
| HtsusCode | 8542.31.0055 |
| Weight | 0.0005g |
Introduction
The XC9536XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of two
Features
- 5 ns pin-to-pin logic delays
- System frequency up to 178 MHz
- 36 macrocells with 800 usable gates
- Available in small footprint packages 44-pin PLCC (34 user I/O pins) 44-pin VQFP (34 user I/O pins) 48-pin CSP (36 user I/O pins) 64-pin VQFP (36 user I/O pins)
- Pb-free available for all packages
- Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS Fast FLASH technology
- Advanced system features
- In-system programmable
- Superior pin-locking and routability with Fast CONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Fast concurrent programming
- Slew rate control on individual outputs
- Enhanced data security features
- Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
- Pin-compatible with 5V-core XC9536 device in the 44-pin PLCC package and the 48-pin CSP package
