مدار مجتمع (آی سی) آی‌سی تعبیه‌شده (پردازنده) پردازندهٔ سیگنال دیجیتال (دی‌اس‌پی)

Product Attributes

Features

• Multicore compute with up to 1000MIPS (8 core) and 4000MIPS (32 core) performance.
• Hardware ResponseTM ports provide flexible, high-performance configurable I/O capability.
• Integrated USB 2.0 PHY for highand full-speed host and device operation.
• Up to 1024KB on-board memory for demanding applications.
• Embedded flash option – up to 2048KB on-board.
• Free software library support to implement your exact mix of peripherals.
• Easy to use with our free xTIMEcomposer Studio™ tools.
• The xCORE-200TM USB family of devices (XU and XUF) extends the popular xCORETM architecture to provide increased performance, memory footprint and flexibility for the most demanding applications.
• xCORE-200 XU/XUF integrates up to two USB 2.0 PHYs (host or device) and implements a dual-issue processor pipeline to boost peak compute performance up to 4000MIPS and 2000MMACS.
• Up to 1024KB on-chip SRAM memory is available. Each member of the xCORE-200 family has an embedded flash option for applications.
• The flexible Hardware Response ports are bonded out to I/O pins as 1bit, 4bit, 8bit, 16bit and 32bit ports, and provide support for serialized and buffered data transfer. Up to 176 general purpose I/O are available for user configuration.
• xCORE-200 is supported by the advanced XMOS xTIMEcomposer StudioTM development environment. A wide range of microcontroller and application libraries are freely downloadable.
• Unlike conventional microcontrollers, xCORE-200 multicore microcontrollers execute multiple realtime tasks simultaneously. The xCORE-200 XU/XUF family includes devices with 8, 10, 12, 16, 24 and 32 cores. Each logical core can execute computational code, advanced DSP code, control software (including logic decisions and executing a state machine) or drive and sample data on the I/O ports.
• xCORE-200TM XUF216 that performs functions similar to those of an RTOS, and hardware that connects the cores directly to I/O pins, ensuring fast processing and extremely low latency. The xTIME scheduler eliminates the use of interrupts and ensures deterministic operation.
• The on-chip SRAM can be accessed in a single cycle, reducing shared memory requirements by passing data directly between tasks executing on logical cores. Similarly the xCONNECT switch is a high-speed network allowing all cores to communicate with each other.
• xCORE-200 multicore microcontrollers include an area of one-time programmable memory with AES support to allow the implementation of secure boot functionality.