Introduction
xCore multicore microcontrollers are unique. Like traditional microcontrollers, they can be programmed in C/C++, but unlike conventional devices, they feature multiple processor cores capable of executing many tasks concurrently and independently. They offer extremely flexible I/O capabilities and a uniquely deterministic architecture that enables tight coupling between cores and the outside world. xCore allows you to tackle complex real-time projects using a simple, flexible, and scalable design flow. Today's embedded applications demand a deterministic microcontroller architecture that can instantly detect and resolve changes as tasks evolve. The architecture must handle multiple concurrent tasks rapidly, minimize jitter, and manage combinations of fast, complex interfaces. It must be easy to integrate with a wide range of components and must be scalable. Traditional real-time systems are interrupt-driven, relying on an RTOS to schedule tasks and manage communications. However, they face numerous challenges, including handling complex I/O streams within acceptable time windows, interrupt latency, kernel processing time, jitter, and memory contention. They are difficult to verify, and the RTOS introduces significant processor and memory overhead. The xCore architecture addresses these issues by removing all features in traditional microcontrollers that introduce non-determinism. Instructions execute in a single cycle; there are no interrupts; there is no conventional bus structure; there is no pipeline; and there is no cache. Many features of an RTOS are integrated directly in hardware: system events are handled via scheduled single-cycle context switches, so applications are unaffected by interrupt jitter. Because multiple processing cores execute independently, tasks are guaranteed to complete within strict timing windows. Tasks can share data without the use of a cache. Each core can run I/O, DSP, and application code, and activity in one task does not affect other tasks. The tight coupling between processor resources and hardware ports delivers I/O events directly to tasks, producing response times up to 100 times faster than traditional microcontrollers. Because xCore devices are deterministic, designers can create predictable systems and precisely combine the peripheral interfaces they need. xCore delivers all the features today's embedded developers require, with performance that interrupt-driven systems simply cannot match. Each xCore device contains one or more processing tiles. Each tile has up to eight independent 32-bit logical cores that run in parallel without interference from one another. A tile also includes the xTIME scheduler, xCONNECT switch, ports, and SRAM. Active cores are guaranteed a minimum level of MIPS performance. Idle cores are not scheduled onto processing resources. Unlike traditional microcontrollers that use memory mapping, logical cores access instructions directly. All instructions complete within a single core cycle, or the core stalls. Cores are triggered by events managed by the xTIME scheduler. Events occurring on I/O pins are fed directly to cores via hardware-responsive ports. Events can also be generated by timers and tasks, serviced by the scheduler with guaranteed behavior. Traditional devices require multiple instruction cycles to respond to an interrupt, during which they save the state associated with the running task and load the new state associated with the higher-priority task to be started. xCore devices respond to events triggered by I/O pins, timers, and tasks rather than interrupts. Because xCore devices can run multiple tasks in parallel, there is no need for one task to interrupt another. A task can handle events by running in parallel with other tasks and waiting for events to occur. The advantages of the XMOS approach include: significantly improved response times to events; and easier reasoning about worst-case execution time, since code is never interrupted during execution. Independent testing shows that xCore devices can respond to a single event within 10 nanoseconds and handle multiple asynchronous real-time events within a worst-case response time of 100 nanoseconds — 100 times faster than traditional real-time systems and, critically, scalable to larger, more integrated systems. By default, each task in an xCore application is placed on a different logical core. This means the task runs independently of other tasks and achieves extremely fast response times while waiting for events. In RTOS terms, every task running on its own core enjoys the highest-priority scheduling provided by the hardware. To reduce resource requirements, lower-priority tasks can share a core through cooperative multitasking. Cooperative multitasking is directly supported by the multicore extensions to C that enable task parallelism on xCore devices. The high-speed xCONNECT network ensures that all tasks on the same tile can communicate with one another.
