آر اف (فرکانس رادیویی) و بی‌سیم آی‌سی آر‌اف‌آی‌دی و کنترل دسترسی

Product Attributes

Introduction

JSMCV520 is a highly integrated read/write card IC for 13.56 MHz contactless communication. It integrates all types of passive contactless communication modes and protocols at 13.56 MHz, supporting multi-layer applications compliant with ISO 14443A.

The internal transmitter of the JSMCV520 can drive the reader antenna for communication with ISO 14443A/MIFARE cards and transponders without requiring any additional circuitry. The receiver section provides a robust and efficient demodulation and decoding circuit for processing ISO 14443A-compatible transponder signals. The digital section handles ISO 14443A framing and error detection (parity & CRC). The JSMCV520 supports the MF1xxS20, MF1xxS70, and MF1xxS50 product series, enabling higher-speed MIFARE contactless communication with bidirectional data transfer rates up to 848 kbit/s.

The JSMCV520 supports read/write mode for the ISO/IEC 14443 A/MIFARE communication protocol, which accommodates multiple transfer speeds and modulation schemes.

For signals transmitted from reader to card, Miller encoding with 100% ASK modulation is used at transfer speeds from 106 kbit/s to 848 kbit/s.

For signals transmitted from card to reader, subcarrier load modulation with BPSK or Manchester encoding is used at transfer speeds from 106 kbit/s to 848 kbit/s.

Communication between the JSMCV520's contactless UART and the external controller uses the ISO/IEC 14443A/MIFARE protocol.

The internal CRC coprocessor calculates values transmitted according to ISO/IEC 14443A Part 3 and checks the parity bit generated during transmission. This bit can be disabled using the parity bit enable function in the Marred register.

The serial peripheral interface (SPI-compatible) supports high-speed communication to the host, capable of handling data streams up to 10 Mbit/s. When communicating with the host, the JSMCV520 operates as a slave, receiving data from the peripheral host to configure registers and exchanging data related to RF interface communication.

The SPI-compatible interface enables high-speed serial communication between the JSMCV520 and the microcontroller, fully compliant with the SPI standard.

The contactless UART supports external host error and frame checking on the bus as required by the protocol at speeds up to 848 kbit/s. It can connect to external circuitry to modulate and demodulate data via the MFIN and MFOUT communication interfaces.

The contactless UART handles the protocol specified for host communication, which is bit- and byte-oriented. It also performs CRC and parity checks in accordance with the supported contactless communication protocols.

The signals output on pins TX1 and TX2 are a 13.56 MHz energy carrier modulated by an envelope signal, capable of directly driving an antenna matched and filtered through passive components. The output signals on TX1 and TX2 can be configured via the TxControlReg register.

Modulation parameters can also be adjusted by varying the driver impedance. The p-driver impedance can be changed by configuring the CWGsPReg and ModGsPReg registers, and the n-driver impedance by configuring the Genre register. Modulation parameters are likewise dependent on the antenna geometry and tuning.

The TxModeReg and Tasseled registers set the data rate and frame rate during transmission. The antenna driver supports different modes and transfer speeds to meet a variety of application requirements.

The JSMCV520 integrates two main modules: the digital module, comprising a state machine and encoder/decoder logic, and the analog module, comprising a modulator and antenna driver, receiver, and amplifier. The interface between the two modules is configured to route interface signals to the MFIN and MFOUT pins.

This topology allows the analog module of the JSMCV520 to be connected to the digital module of other devices.

The JSMCV520 is partitioned into a digital module and an analog module. The digital module includes a state machine and encoder/decoder logic; the analog module includes a modulator and antenna driver, receiver, and amplifier. The interface between the two modules is configured to route interface signals to the MFIN and MFOUT pins. This is achieved by setting the Mouse[3:0] and Diversely[1:0] bits of the Tasseled register and the Cartel[1:0] bits of the Reseller register.

This topology allows part of the analog module circuitry of the JSMCV520 to be connected to the digital module of other devices. The Mouse bits of the Tasseled register can be used to detect signals related to MIFARE and ISO/IEC 14443A.

The most important application of the MFIN and MFOUT pins is in the active antenna concept. The digital module of the JSMCV520 can be connected to an external active antenna circuit. To do so, the Mouse bits must be configured to route the internal Miller-encoded signal to the MFOUT pin (Mouse = 100b), and the Cartel[1:0] bits must be configured to receive a Manchester signal with subcarrier on the MFIN pin (Cartel[1:0] = 01).

It is possible to connect pins TX1, TX2, and RX (with appropriate filtering and matching circuitry) to a passive antenna while simultaneously connecting MFIN and MFOUT to an active antenna. In such a circuit, both RF circuits can be driven by signals from the host processor.

Features

• Highly integrated modulator/demodulator circuit
• Minimal external components required to connect output driver stage to antenna
• Supports ISO/IEC 14443 Type A and MIFARE communication protocols
• Reading distance up to 100mm, depending on antenna size and modulation
• Supports read/write encryption for MF1xxS20, MF1xxS70, and MF1xxS50
• Supports ISO 14443A communication up to 848kbit/s data transfer rate
• Supports MFIN/MFOUT
• Supported interface: Serial Peripheral Interface (SPI)
• 64-byte transmit and receive FIFO buffer
• Flexible interrupt modes
• Hardware reset in low-power mode
• Software power-down mode
• Programmable timer
• Internal oscillator with 27.12MHz crystal connection
• Low-voltage, low-power design at 2.5~3.6V
• CRC and parity checking
• Programmable I/O pins
• On-chip self-test