آر اف (فرکانس رادیویی) و بی‌سیم ماژول‌ فرستنده‌گیرنده و مودم آر اف

Product Attributes

Introduction

The DA14592 is a multi-core wireless microcontroller integrating a latest-generation Arm Cortex-M33 application processor (with floating-point unit), advanced power management, a cryptographic security engine, analog and digital peripherals, a software-configurable protocol engine and radio compliant with Bluetooth Low Energy 5.2, along with 256 kB embedded flash, 96 kB RAM, 16 kB cache RAM, and 288 kB ROM (containing the BLE stack). The embedded flash or SRAM can be externally expanded via QSPI. The DA14592 is optimized for minimum power consumption across radio, active, and sleep modes.

The device features an Arm Cortex-M33 CPU with an eight-region memory protection unit and single-precision FPU, delivering up to 96 dMIPS performance at 64 MHz. This dedicated application processor executes code from embedded flash or RAM through an 8 kB four-way set-associative cache controller. Bluetooth 5.2 and other protocol connectivity is handled by a new software-configurable BLE protocol engine based on the Arm Cortex-M0+, paired with an ultra-low-power radio transceiver capable of +6 dBm output power and -97 dBm receive sensitivity, yielding a total link budget of 103 dB.

A wide range of standard and advanced peripherals enable interaction with other system components and support the development of sophisticated user interfaces and feature-rich applications.

Features

• Bluetooth 5.2, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) compliant
• Flexible processing: 32 kHz to 64 MHz 32-bit Arm Cortex-M33 with 8 kB 4-way set-associative cache and FPU
• Arm Cortex-M0+-based flexibly configurable Bluetooth LE MAC engine with 8 kB 4-way set-associative cache
• Memory: 256 kB embedded flash; 96 kB data SRAM (with retention); 8 kB cache (with retention) each for Cortex-M33 and M0+; 288 kB ROM (includes boot ROM, PKI routines, and Bluetooth LE stack)
• Power/clock management: buck DCDC converter; sleep (ship mode) current <100 nA; programmable BOD threshold; 32 MHz or 64 MHz system clock using multiplier; fast wake from sleep <15 µs
• Application crypto engine supporting AES-256 and SHA-256
• One RTC with 10 ms resolution
• Four general-purpose 24-bit up/down counters with PWM capability
• Analog and digital interfaces: up to 32 GPIOs; 8-channel 10-bit SAR ADC at 2 Msamples/s; ΣΔ ADC at 15-bit @ 1 ksps and 13-bit @ 16 ksps with PGA; QSPI PSRAM/flash interface; 2 UARTs up to 3 Mbps, one extended with ISO7816 support; one SPI+ and one I²C controller at 100 kHz, 400 kHz, or 3.4 MHz; PDM interface with hardware sample rate converter; master/slave I²S/PCM interface supporting up to eight channels; quadrature decoder with 3-axis support
• Radio transceiver: single-wire antenna, no RF matching or RX/TX switching required; high-performance mode: TX output power −22 to +6 dBm, RX sensitivity −97 dBm; low-power mode: TX output power −23 to 4.5 dBm, RX sensitivity −96 dBm
• Packages: WLCSP39, 2.48 × 3.32 mm, 0.42 mm diagonal pitch; FCQFN52, 5.1 × 4.3 mm, 0.4 mm pitch

Applications

• Crowdsourced positioning
• IoT (home, retail, industrial)
• Keyboards
• Gaming mice
• Gaming/AR/VR controllers