آر اف (فرکانس رادیویی) و بی‌سیم آی سی‌ فرستنده‌گیرنده آر اف

Product Attributes

Features

• Ultra-low power at 3.6V: 130μA/MHz IBAT with DC-DC enabled; 110nA sleep current with POR monitor enabled for data retention; 400nA sleep current using smaRTClock (internal LFO); 700nA sleep current using smaRTClock (external XTAL); 2μs wake-up time from any sleep mode
• 12-bit, 16-channel ADC: up to 75ksps in 12-bit mode or 300ksps in 10-bit mode; external pin or internal VREF (no external capacitor required); on-chip PGA allows measurement of voltages up to 2× the reference voltage; autonomous burst mode with 16-bit auto-averaging accumulator; integrated temperature sensor
• Two low-current comparators: programmable hysteresis and response time; configurable as interrupt or reset source
• Internal 6-bit current reference: up to ±500μA with source and sink capability; resolution enhancement via PWM interpolation
• Integrated LCD controller (Si102x only): supports up to 128 segments (32×4); integrated charge pump for contrast control
• Metering-specific peripherals: DC-DC buck converter with dynamic voltage scaling for maximum efficiency (250mW output); sleep-mode pulse counter with programmable switch debounce and pull-up control for direct connection to metering sensors; dedicated data packet processing engine (DPPE) with hardware AES, DMA, CRC, and encoding blocks for accelerating wireless protocols; Manchester and 3-of-6 encoder hardware for efficient implementation of wireless M-Bus specification
• EZRadioPRO transceiver: frequency range 240–960MHz; sensitivity –121dBm; FSK, GFSK, and OOK modulation support; maximum output power +20dBm or +13dBm; RF power consumption: 18.5mA RX, 18mA TX at +1dBm, 30mA TX at +13dBm, 85mA TX at +20dBm; data rate 0.123 to 256kbps; automatic frequency calibration (AFC); antenna diversity and T/R switch control; programmable packet handler; 64-byte TX and RX FIFO; frequency hopping capability; on-chip crystal tuning
• High-speed 8051 µC core: pipelined instruction architecture with 70% of instructions executing in 1 or 2 system clocks
• Memory: up to 128kB flash, in-system programmable with full read/write/erase over the entire supply range; up to 8kB internal data RAM
• Digital peripherals: 53 port I/Os, all 5V-tolerant with high sink current and programmable drive strength; hardware SMBus (I²C-compatible), 2× SPI, and UART serial ports available simultaneously; four general-purpose 16-bit counter/timers; programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer
• Clock sources: precision internal oscillator at 24.5MHz, ±2% accuracy, UART operation support with spread-spectrum mode for EMI reduction; low-power internal oscillator at 20MHz; external oscillator supporting crystal, RC, C, and CMOS clock inputs; smaRTClock oscillator at 32.768kHz crystal or 16.4kHz internal LFO with three independent alarms
• On-chip debug: on-chip debug circuit enables full-speed, non-intrusive in-system debugging (no emulator required) with 4 breakpoints and single-step execution
• Package: 85-pin LGA (6×8mm)