آر اف (فرکانس رادیویی) و بی‌سیم آی سی‌ فرستنده‌گیرنده آر اف

Product Attributes

Features

• Includes ST state-of-the-art patented technology
• Ultra low power radio – 2.4 GHz radio – RF transceiver supporting Bluetooth Low Energy 5.3 specification – Proprietary protocols
• RX sensitivity: -96 dBm (Bluetooth Low Energy at 1 Mbps)
• Programmable output power, up to +10 dBm with 1 dB steps
• Integrated balun to reduce BOM
• Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
• Ultra low power platform with FlexPowerControl
• 1.71 to 3.6 V power supply
• -40°C to 85°C temperature range
• Autonomous peripherals with DMA, functional down to Stop 1 mode
• 140 nA Standby mode (16 wake-up pins)
• 200 nA Standby mode with RTC
• 2.4 μA Standby mode with 64 KB SRAM
• 16.3 μA Stop mode with 64 KB SRAM
• 45 μA/MHz Run mode at 3.3 V
• Radio: Rx 7.4 mA / Tx at 0 dBm 10.6 mA
• Core: Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP, and FPU
• ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 100 MHz, 150 DMIPS)
• Power management: embedded regulator LDO supporting voltage scaling
• Benchmarks 1.5 DMIPS/MHz (Drystone 2.1) 407 CoreMark (4.07 CoreMark/MHz)
• Clock sources: 32 MHz crystal oscillator, 32 kHz crystal oscillator (LSE), Internal low-power 32 kHz (±5%) RC, Internal 16 MHz factory trimmed RC (±1%), PLL for system clock and ADC
• 1 MB flash memory with ECC, including 256 Kbytes with 100 cycles
• 128 KB SRAM, including 64 KB with parity check
• 512-byte (32 rows) OTP
• Rich analog peripherals (independent supply) – 12-bit ADC 2.5 Msps with hardware oversampling
• Communication peripherals: Three UARTs (ISO 7816, IrDA, modem), Two SPIs, Two I2C Fm+ (1 Mbit/s), SMBus/PMBus
• System peripherals: Touch sensing controller, up to 20 sensors, supporting touch key, linear, and rotary touch sensors, One 16-bit, advanced motor control timer, Three 16-bit timers, One 32-bit timer, Two low-power 16-bit timers (available in Stop mode), Two Systick timers, Two watchdogs, 8-channel DMA controller, functional in Stop mode
• Security and cryptography: Arm TrustZone and securable I/O, memories, and peripherals, Flexible life cycle scheme with RDP and password protected debug, Root of trust thanks to unique boot entry and secure hide protection area (HDP), SFI (secure firmware installation) thanks to embedded RSS (root secure services), Secure data storage with root hardware unique key (RHUK), Secure firmware upgrade support with TF-M, Two AES co-processors, including one with DPA resistance, Public key accelerator, DPA resistant, HASH hardware accelerator, True random number generator, NIST SP800-90B compliant, 96-bit unique ID, Active tampers, CRC calculation unit
• Up to 35 I/Os (most of them 5 V-tolerant) with interrupt capability
• Development support – Serial wire debug (SWD), JTAG