آر اف (فرکانس رادیویی) و بی‌سیم سایر آی سی‌ و ماژول‌های آر اف

Product Attributes

Introduction

The AD6649 is a mixed-signal IF receiver featuring a dual-channel 14-bit 250 MSPS ADC and a wideband digital downconverter (DDC), designed to deliver a low-cost, small-footprint, wide-bandwidth, multifunction solution for communications applications. The dual-channel ADC core employs a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features a wide-bandwidth input supporting user-selectable input ranges. An integrated voltage reference simplifies design. A duty cycle stabilizer compensates for variations in ADC clock duty cycle, maintaining excellent converter performance. The ADC data outputs are internally connected directly to the receiver's DDC. The dual-channel digital receiver offers flexible processing capability. Each receive channel consists of four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator, NCO), an optional sample rate converter, a fixed FIR filter, and an f/4 fixed-frequency NCO. In addition to the receiver DDC, the AD6649 provides features that simplify system receiver AGC. Programmable threshold detectors using the ADC fast detect output bits can monitor input signal power. If the input signal level exceeds a programmable threshold, the fast detect indicator asserts high. Due to the extremely short latency of this threshold indicator, users can quickly reduce system gain to prevent overrange conditions at the ADC input. After digital processing, data can be routed directly to 14-bit output ports operating at ANSI or reduced-swing LVDS signal levels. The AD6649 receiver can digitize a wide IF spectrum. Each receiver is designed to simultaneously receive both main channel and diversity channel signals. This IF sampling architecture significantly reduces device cost and complexity compared to traditional analog techniques or less integrated digital approaches. In diversity applications, the final NCO shifts the output center frequency to f/4, resulting in a real-number output data format. Flexible power-down options can substantially reduce power consumption when needed. Setup and control programming is accomplished via a 3-wire SPI-compatible serial interface. The AD6649 is available in a 64-lead LFCSP package, rated for the -40°C to +85°C industrial temperature range.

Features

• SNR: 73.4 dBFS (at 95 MHz bandwidth, 185 MHz Ain, 245.76 MSPS)
• SFDR: 85 dBc (at 185 MHz Ain, 250 MSPS)
• Input noise density: −151.2 dBFS/Hz (at 185 MHz, −1 dBFS Ain, 250 MSPS)
• Total power consumption: 1 W (with fixed-frequency NCO, 95 MHz FIR filter)
• Supply voltage: 1.8 V
• LVDS (ANSI-644 level) output
• 1-to-8 integer input clock divider (max input frequency 625 MHz)
• Integrated dual-channel ADC sample rate up to 250 MSPS
• IF sampling frequency up to 400 MHz
• ADC internal voltage reference
• Flexible input range 1.4 V p-p to 2.1 V p-p (nominal 1.75 V)
• ADC clock duty cycle stabilizer
• 95 dB channel isolation/crosstalk
• Integrated wideband digital processor
• 32-bit complex NCO
• FIR filter with 2 operating modes
• f/4 output NCO for real signal output
• Amplitude detection bit for efficient AGC implementation
• Power-saving shutdown mode
• Decimated interleaved real-signal LVDS data output

Applications

• Communications
• Diversity Radio Systems
• Multi-mode Digital Receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
• General-purpose Software Defined Radio
• Broadband Data Applications