آر اف (فرکانس رادیویی) و بی‌سیم سایر آی سی‌ و ماژول‌های آر اف

Product Attributes

Introduction

The ADF4382 is a high-performance, ultralow jitter fractional-N PLL with an integrated VCO, ideally suited for LO generation in 5G applications or data converter clocking applications. This high-performance PLL has a figure of merit of −239 dBc/Hz, features low 1/f noise, and supports a PFD frequency up to 625 MHz in integer mode, enabling ultralow in-band noise and integrated jitter. The ADF4382 generates frequencies within a fundamental octave range of 11 GHz to 22 GHz, eliminating the need for subharmonic filters. The output divider on the ADF4382 allows generation of a complete output frequency range from 687.5 MHz to 22 GHz. For most data converter clocking applications, the ADF4382 automatically aligns its output to the input reference edge by including the output divider within the PLL feedback loop. For applications requiring deterministic delay or delay adjustment capability, a programmable reference-to-output delay with resolution of less than 1 ps is provided. Reference-to-output delay matching across multiple devices and over the full temperature range enables predictable and precise multichip alignment. The block diagram simplicity of the ADF4382, combined with a simplified SPI register map, an external SYNC input, and repeatable multichip alignment in both integer and fractional modes, reduces development time.

Features

• Output frequency range: 687.5 MHz to 22 GHz
• Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth: 100 Hz to 100 MHz)
• Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
• VCO fast calibration time < 1 μs
• VCO autocalibration time < 100 μs
• Phase noise floor: −156 dBc/Hz at 20 GHz
• Normalized in-band phase noise floor: −239 dBc/Hz
• Normalized 1/f phase noise floor: −287 dBc/Hz
• Maximum phase/frequency detector input frequency: 625 MHz
• Reference input frequency: 4.5 GHz
• Typical spurious f_PFD .. −90 dBc
• Propagation delay temperature coefficient: 0.06 ps/°C
• Adjustment step size: < 1 ps
• Multi-chip output phase alignment
• 3.3 V and 5 V supply voltages
• ADIsimPLL loop filter design tool support
• 7 mm × 7 mm, 48-terminal LGA package
• Operating temperature range: −40°C to +105°C

Applications

• High-performance data converter clocking
• Wireless infrastructure
• Test and measurement