Introduction
The CA-IS302x series are complete bidirectional, dual-channel digital isolators offering 3.75kV_RMS (narrow-body package) or 5kV_RMS (wide-body package) galvanic isolation with a typical CMTI of ±150kV/μs. All devices feature Schmitt-trigger inputs for enhanced noise immunity. Each isolation channel's digital input and output are separated by a silicon dioxide (SiO₂) dielectric barrier, providing superior EMI suppression and low-EMI characteristics. The highly integrated design requires only two external VDDA and VDDB bypass capacitors and pull-up resistors to form a complete I²C isolation interface.
These dual-channel digital isolators support data rates from DC to 2.0MHz. The CA-IS3020 provides two bidirectional, open-drain output isolation channels for bidirectional isolation applications—such as multi-master I²C—that require bidirectional data or clock transmission on a shared bus. The CA-IS3021 provides one unidirectional and one bidirectional isolation channel for single-master I²C isolation, where the unidirectional channel handles clock (SCL) isolation and the bidirectional channel handles data (SDA) isolation. The device's Side A (V_DDA) and Side B (V_DDB) are independently powered with a supply voltage range of 3.0V to 5.5V.
The CA-IS302x series operates over a temperature range of -40°C to +125°C and is available in 8-pin narrow-body SOIC, 8-pin wide-body SOIC, and 16-pin wide-body SOIC packages. The wide operating temperature range and high isolation voltage rating make these devices ideal for harsh industrial environments.
The CA-IS302x dual-channel digital isolators provide a complete bidirectional digital isolation solution, withstanding isolation voltages up to 3.75kV_RMS (narrow-body package) or 5kV_RMS (wide-body package) with a typical CMTI of ±150kV/μs. Unlike a simple parallel combination of two unidirectional isolators, these bidirectional digital isolators fundamentally eliminate the low-level latch-up problem without requiring external anti-deadlock circuitry, effectively saving board space and power consumption. Schmitt-trigger inputs improve noise immunity, and capacitive isolation (SiO₂) is used between logic input and output in each digital channel. Within this series, the CA-IS3020 provides two bidirectional, open-drain digital isolation channels to meet the data and clock isolation requirements of multi-master I²C buses; the CA-IS3021 contains one unidirectional channel and one bidirectional channel for clock (SCL) and data (SDA) line isolation respectively in single-master I²C buses. All devices support data rates up to 2.0MHz; the logic levels on each side of the isolator are determined by the respective supply voltages V_DDA and V_DDB, with a supply range of 3.0V to 5.5V.
The CA-IS302x employs capacitive isolation technology, which—compared to inductive isolation—offers lower power consumption, shorter propagation delay and signal jitter, better EMI suppression, and support for higher signal transmission rates. To implement the bidirectional channel, the CA-IS302x integrates two unidirectional channels within each bidirectional channel; the bidirectional channel output uses an open-drain configuration to comply with standard I²C interface requirements. Side A is intended for connection to I²C nodes with low capacitive loads, with a maximum allowable load capacitance of 40pF; Side B is intended for connection to I²C bus nodes with high capacitive loads, with a maximum allowable load capacitance of 400pF.
In the bidirectional isolation channel, to prevent bus latch-up, Side A output uses a special buffer that sets the logic-low output voltage to approximately 700mV, while the maximum voltage for a logic-low input is 400mV. An internal hysteresis comparator monitors the voltage on the SDAA and SCLA pins to determine whether a logic-low level originates from an external input or from the isolator's own output. This comparator prevents the low level driven by Side A's output from being incorrectly recognized as a logic-low input and propagated to Side B's output, thereby eliminating bus latch-up. Side B uses a conventional buffer with no adjustment to the logic-low voltage. A logic-low input on one side of the isolator pulls the corresponding pin on the other side low.
The I²C bus enables data communication between different ICs (system controllers, remote sensors, actuators, and other circuits) via a 2-wire interface consisting of a data line (SDA) and a clock line (SCL), allowing multiple slave devices to share the same bus without chip-select signals. Because there is only one data line on the bus, operation must be half-duplex—only transmitting or only receiving data at any given time—requiring the data line to support bidirectional transfer. In multi-master systems, both the data line and the clock line must support bidirectional transfer. The CA-IS302x series digital isolators provide either two bidirectional channels (CA-IS3020) or one bidirectional channel for data and one unidirectional channel for clock (CA-IS3021) to meet I²C bus isolation requirements. The I²C bus operates in Standard Mode, Fast Mode, or High-Speed Mode, with maximum rates of 100kbps, 400kbps, and 1.7Mbps (C_bus = 400pF) respectively. The CA-IS302x digital isolators support operating frequencies up to 2.0MHz, satisfying the requirements of the vast majority of I²C applications.
