Introduction
The CA-IS302x series are complete bidirectional, dual-channel digital isolators offering 3.75kV_RMS (narrow-body package) / 5kV_RMS (wide-body package) / 7.5kV_RMS (extra-wide-body package) galvanic isolation and typical CMTI of ±150kV/μs. All devices feature Schmitt-trigger inputs for enhanced noise immunity. The digital input and output of each isolation channel are separated by a silicon dioxide (SiO₂) dielectric barrier, providing high EMI suppression and low EMI emissions. The highly integrated design requires only two external VDDA and VDDB bypass capacitors and pull-up resistors to form a complete I²C isolation interface.
These dual-channel digital isolators support DC to 2MHz data rates. The CA-IS3020 provides two bidirectional, open-drain output isolation channels for multi-master I²C and other applications requiring bidirectional data or clock transmission on a shared bus. The CA-IS3021 provides one unidirectional and one bidirectional isolation channel for single-master I²C isolation applications, where the unidirectional channel is used for clock (SCL) isolation and the bidirectional channel for data (SDA) isolation. Side A (V_DDA) and Side B (V_DDB) are powered independently with a supply voltage range of 3.0V to 5.5V.
The CA-IS302x series operates over a temperature range of -40°C to +125°C and is available in 8-pin narrow-body SOIC, 8-pin/16-pin wide-body SOIC, and 8-pin extra-wide-body SOIC packages. The wide operating temperature range and high isolation voltage rating make these devices well suited for harsh industrial environments.
The CA-IS302x dual-channel digital isolators provide complete bidirectional digital isolation, withstanding isolation voltages up to 3.75kV_RMS (narrow-body package), 5kV_RMS (wide-body package), and 7.5kV_RMS (extra-wide-body package), with typical CMTI of ±150kV/μs. Unlike simple back-to-back unidirectional isolator solutions, these bidirectional digital isolators fundamentally eliminate the low-level latch-up problem without requiring external anti-lockup circuitry, effectively saving board space and reducing power consumption. Schmitt-trigger inputs enhance noise immunity, and capacitive isolation (SiO₂) is used between the logic input and output of each digital channel. In this series, the CA-IS3020 provides two bidirectional, open-drain digital isolation channels to meet the data and clock isolation requirements of multi-master I²C buses; the CA-IS3021 includes one unidirectional channel and one bidirectional channel for clock (SCL) and data (SDA) line isolation respectively in single-master I²C bus applications. All devices support data rates up to 2MHz. The logic levels on each side of the isolator are determined by the supply voltages V_DDA and V_DDB, with a supply range of 3.0V to 5.5V.
The CA-IS302x employs capacitive isolation technology, which compared to inductive isolation offers lower power consumption, shorter propagation delay and signal jitter, better EMI suppression, and support for higher signal transmission rates. To implement bidirectional transmission channels, the CA-IS302x integrates two unidirectional channels within each bidirectional channel. The bidirectional channel outputs are open-drain to meet standard I²C interface requirements. Side A is intended for connection to I²C nodes with low capacitive loads, supporting a maximum load capacitance of 40pF; Side B is intended for connection to I²C bus nodes with high capacitive loads, supporting a maximum load capacitance of 400pF.
In bidirectional isolation channels, to prevent bus lockup, Side A output uses a special buffer that sets the logic-low output voltage to approximately 700mV, while the maximum logic-low input threshold voltage is 400mV. An internal hysteresis comparator monitors the voltage on the SDAA and SCLA pins to determine whether a logic-low level originates from an external input or from the isolator's own output. This comparator-based approach prevents the low level driven by Side A's output from being falsely interpreted as a logic-low input and forwarded to Side B's output, thereby eliminating bus lockup. Side B uses a conventional buffer with no adjustment to the logic-low output voltage. A logic-low input on one side of the isolator pulls the corresponding pin on the other side low.
The I²C bus enables data communication between different ICs (system controllers, remote sensors, actuators, and other circuits) via a 2-wire interface consisting of a data line (SDA) and a clock line (SCL). Multiple slave devices can be connected to the same bus without requiring chip select signals. Since there is only one data line on the bus, half-duplex operation is required — only transmitting or only receiving at any given time — so the data line must support bidirectional transfer. In multi-master systems, both the data line and clock line must support bidirectional transfer. The CA-IS302x series digital isolators provide either two bidirectional channels (CA-IS3020) or one bidirectional channel for data and one unidirectional channel for clock (CA-IS3021) to meet I²C bus isolation requirements. The I²C bus operates in Standard Mode, Fast Mode, or High-Speed Mode, with maximum rates of 100kbps, 400kbps, and 1.7Mbps (C_bus = 400pF), respectively. The CA-IS302x digital isolators support operating frequencies up to 2MHz, satisfying the requirements of the vast majority of I²C applications.
The CA-IS302x isolation ICs provide complete digital isolation across two different power domains. By breaking ground loops, they prevent high common-mode transients or fault voltages from damaging equipment. These devices require no special power-up sequencing; the logic levels of Side A and Side B signals are determined by V_DDA and V_DDB respectively. The SDAA, SCLA, SDAB, and SCLB pins are open-drain outputs and must be connected to their respective supplies via external pull-up resistors to ensure correct logic-high output levels. Side B output guarantees correct logic-low levels at a maximum sink current of 35mA; Side A output allows a maximum sink current of 3.5mA. Accordingly, the minimum pull-up resistor values must ensure that the Side A signal line input current ≤3.5mA and the Side B signal line input current ≤35mA. The maximum pull-up resistor values are determined by the load capacitance and rise time requirements.
To minimize power supply ripple and reduce interference, a low-ESR bypass capacitor of at least 0.1μF should be placed between VDDA and GNDA, and between VDDB and GNDB. Bypass capacitors should be placed as close as possible to the device's power supply pins. In addition, PCB input and output signal traces should be kept as short as possible, vias should be avoided on signal traces to minimize parasitic inductance. No ground planes or signal traces should be routed beneath the isolator, as any electrical or metal connections between the "A" side and "B" side will degrade the isolation voltage rating. PCB designers should follow these basic guidelines to achieve optimal digital isolation performance.
