مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

The KSZ8993M, a highly integrated Layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes tag/port-based VLAN, quality of service (QoS) priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KSZ8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. Both PHY units support 10BASE-T and 100BASETX. In addition, one of the PHY unit supports 100BASE-FX. The KSZ8993ML is the single supply version with all the identical rich features of the KSZ8993M.

Features

• Proven Integrated 3-Port 10/100 Ethernet Switch
  • 2nd generation switch with three MACs and two PHYs fully compliant to IEEE 802.3u standard
  • Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and a store-and-forward architecture
  • Full duplex IEEE 802.3x flow control (pause) with force mode option
  • Half-duplex back pressure flow control
  • Automatic MDI/MDI-X crossover with disable and enable option
  • 100BASE-FX support on port 1
  • MII interface supports both MAC mode and PHY mode
  • 7-wire serial network interface (SNI) support for legacy MAC
  • Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed
• Comprehensive Configuration Register Access
  • Serial management interface (SMI) to all internal registers
  • MII management (MIIM) interface to PHY registers
  • SPI and I²C Interface to all internal registers
  • I/O Pins strapping and EEPROM to program selective registers in unmanaged switch mode
  • Control registers configurable on the fly (portpriority, 802.1p/d/q, AN…)
• QoS/CoS Packet Prioritization Support
  • Per port, 802.1p and DiffServ-based
  • Re-mapping of 802.1p priority field per port basis
• Advanced Switch Features
  • IEEE 802.1q VLAN support for up to 16 groups (full-range of VLAN ID)
  • VLAN ID tag/untag options, per port basis
  • IEEE 802.1p/q tag insertion or removal on a per port basis (egress)
  • Programmable rate limiting from 0Mbps to 100Mbps at the ingress and egress port, rate options for high and low priority per port basis
  • Broadcast storm protection with % control (global and per port basis)
  • IEEE 802.1d spanning tree protocol support
  • Upstream special tagging mode to inform the processor which ingress port receives the packet
  • IGMP v1/v2 snooping support for multicast packet filtering
  • Double-tagging support
• Switch Management Features
  • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII
  • MIB counters for fully compliant statistics gathering, 34 MIB counters per port
  • Loopback modes for remote diagnostic of failure
• Low Power Dissipation: <0.8 Watts (includes PHY transmit drivers)
  • Full-chip hardware power-down (register configuration not saved)
  • Per port based software power-save on PHY (idle link detection, register configuration preserved)
  • 0.18um CMOS technology
  • Voltages: Core 1.8V I/O and Transceiver 3.3V Use K8993ML for 3.3V only operation
• Available in 128-Pin PQFP

Applications

• Universal Solutions
  • Broadband gateway / Firewall / VPN
  • Integrated DSL or cable modem multi-port router
  • Wireless LAN access point + gateway
  • Residential and enterprise VoIP gateway/phone
  • Set-top/game box
  • Home networking expansion
  • Standalone 10/100 switch
  • FTTx customer premises equipment
  • Fiber broadband gateway
• Upgradeable Solutions
  • Unmanaged switch with future option to migrate to a managed solution
  • Single PHY alternative with future expansion option for two ports
• Industrial Solutions
  • Applications requiring port redundancy and port monitoring
  • Sensor devices in redundant ring topology