مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

The Micrel KS8993F is the first single chip Fast Ethernet Media Converter with built-in OAM functions. The KS8993F integrates three MACs, two PHYs, OAM, frame buffer and high performance switch into a single chip. It is ideal for use in 100BASE-FX to 10BASE-T or 100BASETX conversion in the FTTx market. The KS8993F provides remote loop back and OAM (Operation, Administration and Maintenance) to manage subscriber access network from carrier center side to terminal side. The KS8993F supports advanced features such as rate limiting, force flow control and link transparency. The KS8993F with built-in Layer 2 switch capability will filter packets and forward them to valid destination. It will discard any unwanted frames and frames with invalid destination. The KS8993FL is the single supply version with all the identical rich features of the KS8993F.

Features

• First single-chip 10BASE-T/100BASE-TX to 100BASE-FX media converter with TS-1000 OAM
• Integrated 3-Port 10/100 Ethernet Switch with 3 MACs and 2 PHYs
• Unique User Defined Register (UDR) feature brings OAM to low cost/complexity nodes
• Automatic MDI/MDI-X crossover with disable and enable option
• Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC Address lookup table and a store-and-forward architecture
• Comprehensive LED indicator support for link, activity, full/half duplex and 10/100 speed
• Full complement of MII/SNI, SPI, MIIM, SMI and I2C interfaces
• Low Power Dissipation: < 800mW (includes PHY transmit drivers)
• Supports OAM sub-layer which conforms to TS-1000 specification from TTC (Telecommunication Technology Committee)
• Sends and receives OAM frames to Center or Terminal side
• Loop back mode to support loop back packet from Center side to Terminal side
• Far-end fault detection with disable and enable
• Link Transparency to indicate the link down from link partner
• Comprehensive Configuration Register access: Serial Management Interface (SMI) to all internal registers
• MII Management (MIIM) Interface to PHY registers
• SPI and I2C Interface to all internal registers
• I/O Pins Strapping and EEPROM to program selective registers in unmanaged switch mode
• Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…)
• QoS / CoS packets prioritization support
• per-port, 802.1p and DiffServ based
• Re-mapping of 802.1p priority field per-port basis
• IEEE 802.1q VLAN support for up to 16 groups (full range of VLAN ID)
• VLAN ID tag/untag options, per-port basis
• IEEE 802.1p/q tag insertion or removal on a per port basis (egress)
• Programmable Rate Limiting from 0 to 100 Mbps at the ingress & egress port, rate options for high & low priority, per port basis
• Broadcast storm protection with % control (global & per port basis)
• Double Tagging support
• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII
• MIB (Management Information Base) counters for fully compliant statistics gathering, 34 MIB counters per port
• Full-chip hardware power-down (register configuration not saved)
• Per-port based software power-save on PHY (idle link detection, register configuration preserved)
• 0.18um CMOS technology
• Voltages: Core 1.8V I/O and Transceiver 3.3V
• Available in 128-pin PQFP