مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Features

• The CPS-1432 (80HCPS1432) is a RapidIO Specification (Rev. 2.1) compliant Central Packet Switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other RapidIO-based devices. It can also be used in RapidIO backplane switching.
• Supports Serial RapidIO (S-RIO) packet switching (unicast, multicast, and an optional broadcast) from any of its 14 input ports to any of its 14 output ports.
• 32 bidirectional S-RIO lanes
• Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
• Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
• Support Level I defined short or long haul reach, and Level II defined short-, medium-, or long-run reach for each PHY speed
• Error Management Extensions support
• Software-assisted error recovery, supporting hot swap
• Provides I²C port for maintenance and error reporting
• Master or Slave operation
• Master allows power-on configuration from external ROM
• Master mode configuration with external image compressing and checksum
• 160 Gbps peak throughput
• Non-blocking data flow architecture
• Configurable for Cut-Through or Store-and-Forward data flow
• Very low latency for all packet lengths and load conditions
• Internal queuing buffer and retransmit buffer
• Standard transmitter- or receiver-controlled flow control
• Global routing or Local Port routing capability
• Supports up to 40 simultaneous multicast masks, with broadcast
• Performance monitoring counters for performance and diagnostics analysis. Per input port and output port counters
• Transmitter pre-emphasis and drive strength + receiver equalization provides best possible signal integrity
• Embedded PRBS generation and detection with programmable polynomials support
• Bit Error Rate testing
• Packet Trace/Mirror. Each input port can copy all incoming packets matching user-defined criteria to a “trace” output port.
• Packet Filter. Each input port can filter (drop) all incoming packets matching user-defined criteria.
• Device configurable through any of S-RIO ports, I²C, or JTAG
• Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
• Lidless 784-FCBGA Package: 25 X 25 mm, 1.0 mm ball pitch

Applications

• High-performance computing
• Video and imaging