مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

8-Bit CPU plus ROM, RAM, I/O, Timer and Clock in a Single Package One 8-Bit Status and Two Data Registers for Asynchronous Slave-to-Master Interface DMA, Interrupt, or Polled Operation Supported 1024 x 8 EPROM, 64 x 8 RAM, 8-Bit Timer/Counter, 18 Programmable I/0 Pins Fully Compatible with All Microprocessor Families 3.6 MHz 8741A-8 Available Expandable I/0 RAM Power-Down Capabllity Over 90 Instructions: 70% Single Byte Available in EXPRESS -- Standard Temperature Range -- Extended Temperature Range

The Intel 8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit microprocessor systems, It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, I/O ports, timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to function as a peripheral controller in MCS-48, MCS-80, MCS-85, MCS-86, and other 8-bit systems.

The UPl-41A has 1K words of program memory and 64 words of data memory ori-chip.

The device has two 8-bit, TTL compatible I/O ports and two test inputs. Individual port lines can function as either inputs or outputs under software control. I/0 can be expanded with the 8243 device which is directly compatible and has 16 I/O lines. An 8-bit programmable timer/counter is included in the UPl device for generating timing sequences or counting external inputs. Additional UPl features include: single 5V supply, single-step mode for debug and dual working register banks.

Because it's a complete microcomputer, the UPl provides more flexibility for the designer than conventional LSI interface devices. It is designed to be an efficient controller as well as an arithmetic processor.

Features

• Two Data Bus Buffers, one for input and one for output. This allows a much cleaner Master/Slave protocol.
• 8 Bits of Status
  • sT̅₄..sT̅₇ are user definable status bits. These bits are defined by the "MOV STS, A" single byte, single cycle instruction. Bits 4 - 7 of the accumulator are moved to bits 4 - 7 of the status register. Bits 0 - 3 of the status register are not affected.
  • MOV STS, A Op Code: 90H
• RD and W̅A̅ are edge triggered. IBF, OBF, F₁ and INT change internally after the trailing edge of RD or WR.
• P₂₄ and P₂₅ are port pins or Buffer. Flag pins which can be used to interrupt a master processor. These pins default to port pins on Reset.
  • If the "EN FLAGS" instruction has been executed, P₂₄ becomes the OBF (Output Buffer Full) pin. A "1" written to P₂₄ enables the OBF pin (the pin outputs the OBF Status Bit). A "0" written to P₂₄ disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is available from the UPl41A (in Output Data Bus Buffer).
  • If "EN FLAGS" has been executed, P₂₅ becomes the IBF (Input Buffer Full) pin. A "1" written to P̅₂₅ enables the I̅B̅F̅ pin (the pin outputs the inverse of the IBF Status Bit). A "0" written to P₂₅ disables the IBF pin (the pin remains low). This pin can be used to indicate that the UPl is ready for data.
  • EN FLAGS Op Code: OF5H
• P₂₆ and P₂₇ are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset.
  • If the "EN DMA" instruction has been executed, P₂₆ becomes the DRQ (DMA Request) pin. A "1" written to P₂₈ causes a DMA request (DRQ is activated). DRQ is deactivated by DACK·RD, DACK·WR, or execution of the “EN DMA" instruction.
  • If "EN DMA" has been executed, P₂₇ becomes the DACK (DMA Acknowledge) pin. This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers.
  • DMA Handshake Capability
  • EN DMA Op Code: OE5H

Applications

• keyboard scanning
• printer control
• display multiplexing