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ADI AD6624AS

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ADI AD6624AS

Manufacturer ADI
Mfr. Part Number AD6624AS
Electland Part Code 172571
Electland Part Number NYE_AD6624AS
Category Specialized ICs
Description Specialized ICs RoHS
Datasheet Download

Product Attributes

Category Integrated Circuits (ICs) Specialized ICs
Operating Temperature -40℃~+85℃
Weight 0.5g

Introduction

The AD6624A is a four-channel (quad) digital Receive Signal Processor (RSP) featuring four cascaded signal processing elements: a frequency translator, two fixed-coefficient decimation filters, and one programmable-coefficient decimation filter. The AD6624A is part of Analog Devices' SoftCell® multicarrier transceiver chipset, designed for compatibility with Analog Devices' high sample rate IF-sampling ADC family (AD6640/AD6644 12-bit and 14-bit). The SoftCell receiver includes a digital receiver capable of digitizing an entire carrier spectrum and digitally selecting carriers of interest for tuning and channel selection. This architecture eliminates redundant radio equipment in wireless base station applications. High dynamic range decimation filters provide a wide range of decimation rates. The RAM-based architecture facilitates reconfiguration for multi-mode applications. The decimation filters remove unwanted signals and noise from the channel of interest. When the bandwidth occupied by the channel of interest is less than the bandwidth of the input signal, this suppression of out-of-band noise is referred to as "processing gain." By using large decimation factors, this "processing gain" can improve the SNR of the ADC by 30 dB or more. Additionally, the programmable RAM coefficient filter allows anti-aliasing, matched filtering, and static equalization functions to be combined in a single cost-effective filter. The AD6624A is compatible with standard ADC converters such as the AD664x, AD9042, AD943x, and AD922x series data converters. The AD6624A is also compatible with the AD6600 diversity ADC, providing a path to reduced cost and size.

Features

  • 100 MSPS wideband input (14-bit linear plus 3-bit RSSI)
  • Dual high-speed data input ports
  • Four independent digital receivers in a single package
  • Digital resampling for non-integer decimation rates
  • Programmable decimation FIR filter
  • Programmable attenuator control for clipping prevention and external gain range adjustment via level indicator
  • Flexible control for multi-carrier and phased array applications
  • 3.3 V I/O, 2.5 V CMOS core
  • User-configurable built-in self-test (BIST)
  • JTAG boundary scan

Applications

Multi-carrier, multi-mode digital receivers (GSM, IS136, EDGE, PHS, IS95), microcell and picocell systems, wireless local loop, smart antenna systems, software-defined radio, indoor cordless telephony

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