| Manufacturer | TI |
|---|---|
| Mfr. Part Number | CA3142E |
| Electland Part Code | 172509 |
| Electland Part Number | NYE_CA3142E |
| Category | Specialized ICs |
| Description | Video Processor 16-PDIP |
| Datasheet | Download |
| Category | Integrated Circuits (ICs) Specialized ICs |
|---|---|
| type | Video Processor |
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300", 7.62mm) |
| Supplier Device Package | 16-PDIP |
| Packaging | PDIP-16 |
| Tariff Active | False |
| ReachStatus | REACH not applicable |
| RohsStatus | Not Applicable |
| MoistureSensitivityLevel | 3 (168 Hours) |
| ExportControlClassNumber | EAR99 |
| HtsusCode | 8542.39.0001 |
| Weight | 0.5g |
An AGC sample-and hold system generates control voltages proportional to the video level. The sync-tip voltage is compared to an internal reference voltage during the horizontal synchronization (retrace) interval. The control voltages(AGC outputs)are supplied to the tuner's RF stage and the IF amplifier to maintain the video level at a constant value. The composite positive and negative output sync signals are developed across a low impedance source (totem-pole circuit) at an amplitude of approximately 20 volts peak-to-peak. Video Chain and Impulse Noise Inverter - The input video signal applied at Terminal 8 is white “positive" with a required amplitude in the range of 2 to 4 volts. The DC level of the sync peaks, AGC threshold voltage (VrH) is approximately 5 volts. The level is maintained at 5 volts by the AGC loop in the circuit, comprised of the CA3142 and the TV receiver RF and IF amplifiers. A low source impedance video signal is available from the emitter of Q1 (Terminal 9 in Fig. 2). The external resistor Rx1 in Fig. 9 reduces the dissipation of Q1. The emitter-follower output of Q1 is directly coupled to a differential comparator stage (Q2, Q3). Unless a negative-going pulse is present, Q2 functions as an emitter follower and also cuts off transistors Q3, Q5, and Q12. The output of Q2 is applied through a signal delay network, consisting of transistor Q60 and associated resistors, to the Darlington followers (Q13 and Q14). The delayed video signal at Q14 is fed via its emitter to an AGC comparator Q19 and to the junction of a noise-cancelling amplifier stage (Q16). The noise-cancelled video signal is inverted and amplified by Q16 and then connected to a Darlington emitter-follower output stage (Q57, Q58). If impulse noise is present on the video signal, Q3 conducts and turns on transistors Q5 and Q12. Q5 inverts and “stretches" the noise pulse width. The output of Q5 is applied to an emitter follower stage (Q12). The signal from Q12, in turn, is applied to the summing junction to the noise-cancelling amplifier Q16. The noise pulse, which has now been amplified, inverted and stretched, is added to the delayed video signal from the emitter of Q14. Because the video signal has been delayed approximately 300 nanoseconds and the noise pulse has been widened ("stretched") approximately 500 nanoseconds, the output of the combined signal no longer contains impulse noise signals. The derived noise-gating pulse “surrounds" and effectively eliminates the effects of the impulse noise. The noise-cancelled video signal, amplified and buffered, is available at Terminal 5 for use in the sync-separator stage. The peak-to-peak amplitude of the noise-cancelled output signal is approximately twice the amplitude of the input video signal at Terminal 8. Sync Separator (See Fig. 3) — The sync separator stage (Q56) clamps the detected sync tips to a fixed reference voltage (≡ 0.7 V) across its base-emitter junction, and amplifies a portion of the sync signal to provide dual polarity sync-signal outputs at Terminals 2 (negative) and 3 (positive). The output signals are derived from low-impedance complementary emitter-follower stages; a base current of 100 microamperes into Terminal 4 is sufficient to generate full-amplitude sync signals. The choice of coupling the noise-cancelled video-signal from the emitter-follower (Terminal 5) to the sync separator (Terminal 4) is a user option. Fig. 4 shows three typical coupling networks. Fig. 5 illustrates the operation of the AGC circuits. An input ramp signal, simulating the potential to which the AGC filter capacitor may be charged, is applied to Terminal 11. The forward IF AGC output voltage appears at Terminal 13. Under low-signal level conditions (represented by A to B in Fig. 5) the output level is approximately 1.4 volts less than the voltage applied to Terminal 12. The circuit designer should select the voltage at Terminal 12 to provide the maximum IF gain required for the system. At intermediate signal level conditions (represented by B to C in Fig. 5), the iF AGC signal follows the AGC filter potential. The tuner(s) will operate at maximum gain for good signal-to-noise ratios at these equivalent input signal levels. Point C is a turnover point determ
| QTY | USD | TOMAN |
|---|---|---|
| 1+ | $1.68 | 466,460 تومان |
| 200+ | $0.6732 | 186,920 تومان |
| 500+ | $0.6505 | 180,610 تومان |
| 1000+ | $0.6395 | 177,560 تومان |