مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

The Intel IXF1002 dual-port Gigabit Ethernet Media Access Controller (MAC) provides two independent 1000 Mb/s intelligent, high-performance MAC ports. It includes Gigabit Physical Coding Sublayer (GPCS) interface network management support and is optimized for switch applications. The IXF1002 handles SNMP and RMON management counter sets, accessible via a general-purpose CPU 8/16-bit interface, which is also used for mode programming. Each MAC port includes a 4 Kbyte packet receive FIFO and a 2 Kbyte packet transmit FIFO. All packets are transferred through a high-performance general-purpose IX bus interface.

Features

• Dual independent 1000 Mb/s Ethernet MAC ports
• GPCS functionality for 1000BASE-X connectivity
• SNMP and RMON counter handling
• Memory bus bandwidth up to 5.12 Gbps
• Variable bus speed from 33 MHz to 80 MHz
• 64-bit bus with three operating modes: Full Mode (64-bit for transmit or receive), Split Mode (32-bit lower for receive, 32-bit for transmit), Narrow Mode (32-bit for transmit or receive)
• Per-port independent 2 Kbyte transmit FIFO and 4 Kbyte receive FIFO
• Little-endian or big-endian byte order support
• Receive packet segmentation on byte boundaries (replay functionality)
• Programmable transmit and receive bus thresholds
• Optional additional packet status
• Packet transfer completion before CPU interrupt request processing
• Early address filtering for packet header pre-processing
• On-chip IEEE P802.1Q Virtual Bridged LAN (VLAN) tag append, strip, and replace
• Ignore or halt transmit options on packet transfer error
• Programmable auto-discard of bad received packets (e.g., CRC errors and oversized packets)
• System notification on bad packets detected on FIFO bus
• Programmable inter-packet gap (IPG)
• Independent per-port operation
• IEEE 802.3x flow control support
• Standard GPCS interface (10b interface) support
• Standard GMII interface support
• 1000BASE-SX, 1000BASE-LX, 1000BASE-CX, and 1000BASE-T connectivity support
• Programmable CRC generation and removal
• Auto-negotiation link protocol for 1000BASE-X
• Full-duplex operation only
• IEEE 802.3z compliant
• Jumbo frame support up to 64 Kbytes
• Fully programmable independent port access via dedicated general-purpose CPU port
• Interrupt programming support
• 8-bit or 16-bit bus for register access
• CPU and FIFO interfaces compatible with IXF440 multi-port 10/100 Mbps Ethernet controller and IXP1200 network processor
• Internal and external loopback capability
• Software reset support
• JTAG boundary scan support
• Low-power 3.3 V, 5 V-tolerant CMOS implementation
• 304-ESBGA package

Applications

• Switch applications