مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

The AM29C841A and AM29C843A CMOS bus interface latches are designed to eliminate the extra devices required to buffer individual latches and to provide additional data width for wider address/data paths or buses carrying parity. The AM29C800A latches are fabricated using AMD's proprietary CS11SA CMOS process, featuring a typical propagation delay of 5 ns and output current drive of 48 mA. The AM29C841A is a 10-bit buffered version of the popular "373 function." The AM29C843A is a 9-bit buffered latch with preset (PRE) and clear (CLR) functions, making it ideal for parity bus interfaces in high-performance microprogrammed systems. The AM29C841A and AM29C843A incorporate AMD's proprietary edge-controlled outputs to minimize simultaneous switching noise (ground bounce), undershoot, and overshoot. By controlling output transient currents, ground bounce and output ringing are significantly reduced. The improved AMD outputs deliver stable, usable voltage levels in less time than non-controlled outputs. In addition, the speed degradation caused by an increased number of switching outputs is also reduced. These slew-rate control advantages yield significant improvements in system performance, despite a slight increase in device propagation delay. A unique I/O circuit employs n-channel pull-up transistors (eliminating the parasitic diode to Vcc) to provide high-impedance outputs during power-down and power-up/power-down sequencing, ensuring glitch-free operation for card-edge and other active bus applications. The AM29C841A and AM29C843A are available in standard package options: DIP, PLCC, and SOIC.

Features

• High-speed parallel latch
• D-Y propagation delay typical = 5 ns
• Low standby power consumption
• Very high output drive
• Iₒ₁ = 48 mA (commercial)
• Ultra-wide (9-bit and 10-bit) data paths
• Proprietary edge-rate controlled outputs significantly reduce undershoot, overshoot, and ground bounce
• Power-up/power-down disable clear circuit for glitch-free power sequencing
• Power-down capability in tri-state, ideal for card-edge interface applications
• Minimal speed degradation when switching multiple outputs simultaneously
• Data input path typical hysteresis 200 mV
• JEDEC FCT compliant

Applications

• Card edge interface
• High-performance microprogrammed system