مدار مجتمع (آی سی) آی سی‌کاربرد ویژه

Product Attributes

Introduction

The '19 and '20 are decade shift counters with active LOW 1-of-10 decoded outputs. The decoded shift counter technique provides ten mutually exclusive, glitchless outputs. The edge-triggered counter is advanced on each LOW-to-HIGH transition of the Clock input (CP). When the Clock Enable (CE), Synchronous Reset (SR (overline)), Master Reset (MR) are HIGH, the device is sequenced via the Clock thru output states 0 (overline) - 0₀ (overline) successively. The active HIGH Count Enable (CE) input is gated with the Clock and can be interchanged with Clock for layout convenience. A LOW on the CE input inhibits the Clock and stops the counter. By returning one of the outputs to the CE input, the device will sequence up to that output state and stop until reset with the Master Reset. Because the CE input is gated with the CP input, it cannot be changed from LOW to HIGH while the CP is HIGH. The active Low Synchronous Reset ((S + 1) (overline)) is used to reset the counter to zero (returning the output to the 0₀ state) in response to the LOW-to-HIGH transition of the Clock. Any sequence between "two" and "ten" can be obtained by connecting the last desired output to the SR input. This method of truncating the sequence produces a series of pulses of equal duration as long as the clock frequency remains constant. A LOW on the Master Reset (MR) overrides all other input conditions and resets the counter to zero. As long as the MR is LOW, all of the outputs are HIGH. When the MR (overline) goes from LOW to HIGH, the zero output (0₀ (overline)) goes LOW. This MR gating with the 0₀ (overline) output insures complete system resetting or initialization before the first output in the sequencer is activated. For low frequency applications (below 1.0 MHz) the MR can be used in lieu of the SR for truncating the count sequence. If the input CP rise time is very slow (over 100 ns), the MR input should be used to reset the counter to avoid mis-triggering. This is accomplished by returning the next higher output to the MR pin. After the desired sequence is completed, the next clock pulse will reset the counter and enable the first output within 50 ns. The outputs of the '19 are standard TTL totem pole type which can drive up to ten standard TTL unit loads. The outputs of the '20 are DTL resistor pull-up type for applications requiring wired-AND connections. The on-chip pull-up resistors, (about 3 kΩ) of the '20 eliminate the need for external resistors normally required by open collector outputs. Up to eight '20 outputs can be tied together with enough sink current capability left to drive one standard TTL input or five 93L or 54LS/74LS inputs. The '19 and '20 will normally require initialization after power is first applied. A LOW pulse on the Master Reset (or a LOW on the Synchronous Reset in conjunction with a clock pulse) will reset the 5-bit register and activate Output 0 (overline)₀. If initialization is not possible or not required, an error correction circuit is provided to detect some of the 22 unused states and return the counter to the proper sequence within ten clock cycles.