مدار مجتمع (آی سی) آی‌سی صوتی ویژه

Product Attributes

Introduction

The STA020 is a monolithic CMOS device which encodes and transmits audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface standards. It supports 96 kHz sample rate operation. The STA020 accepts audio and digital data which is then multiplexed, encoded and driven onto a cable. The audio serial port is double-buffered and capable of supporting a wide variety of formats. The STA020 multiplexes the channel, user, and validity data directly from the serial input pins with dedicated input pins for the most important channel status bits.

The STA020 is a monolithic CMOS circuit that encodes and transmits audio and digital data according to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The chip accepts audio and control data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through a transformer, to a transmission line. The STA020 has dedicated pins for the most important control bits and a serial input port for the C, U and V bits. The STA020 accepts 16 to 24-bit audio samples through a serial port configured in one of seven formats; provides several pins dedicated to particular channel status bits and allows all channel status, user and validity bits to be serially input through port pins. This data is multiplexed, the parity bit is generated and the bit stream is biphase-mark encoded and driven through an RS422 line driver. The STA020 operates as a professional or consumer interface transmitter selectable by pin 2, PRO. As a professional interface device, the dedicated channel status input pins are defined according to the professional standard, and the CRC code (C.S. byte 23) can be internally generated. As a consumer device, the dedicated channel status input pins are defined according to the consumer standard. A submode provided under the consumer mode is compact disk, CD, mode. When transmitting data from a compact disk, the CD subcode port can accept CD subcode data, extract channel status information from it, and transmit it as user data. The master clock, MCK, controls timing for the entire chip and must be 128×Fs. As an example, if stereo data is input to the STA020 at 44.1kHz, MCK input must be 128 times that or 5.6448 MHz.

The differential line drivers for STA020 are low skew, low impedance, differential outputs capable of driving 110 Ohm transmission lines. (RS422 line driver compatible). They can also be disabled by resetting the device (RST = Low).

The audio serial port is used to enter audio data and consists of three pins: SCK, SDATA and FSYNC, SCK clocks in SDATA, which is double buffered, while FSYNC delineates the audio samples and may indicate the particular channel, left or right. To support many different interfaces, M2, M1 and M0 select one of seven different formats for the serial port. The serial input pins for channel status (C), user (U), and validity (V) are sampled during the first bit period after the active edge of FSYNC for all formats except Format 4. Format 4 is sampled during the second bit period (coincident with the MSB). The C, U, and V bits are transmitted with the audio sample entered before FSYNC edge that sampled it.

Features

• Monolithic digital audio interface transmitter
• 3.3 V supply voltage
• Supports: – AES/EBU, IEC 958 S/PDIF, & EIAJ CP - 340 Professional and consumer formats
• Parity bits and CRC codes generated
• Transparent mode allows direct connection of STA020 and STA120